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2D and 3D Board Viewers
2D and 3D board design files will be posted in this page as they become available, plan is to have all the current boards listed here. There are some good free Gerber viewers out in cyberspace, Gerber in this context has nothing to do with baby food, so three of these Gerber RS-274X file viewers are presented here:
  1. Part of the gplEDA project, Gerbv is a pretty good 2D Gerber viewer, click on the picture on the left below to see an example Gerbv screen. Gerbv projects are supplied as zipped archives, the user extracts archive contents in a folder of choice and double-clicks on the file with *.gvp extension to start the utility. Gerbv can be downloaded and installed from here: https://sourceforge.net/projects/gerbv/. After installation you might want to try this sample, and if so click to download the GERBV.CDi3M1.zip project.
  2. Part of the Pentalogix CAM software suite Viewmate, 3D Board Viewer provides much more realistic output of what the physical board will look like, particularly useful before the design files are sent out to manufacture. The viewer runs on Windows Vista and above and exists as both 32-bit and 64-bit versions. 3D board projects are supplied as zipped archives, however, no extraction is necessary as the utility opens *.zip archives. The 32-bit installer is here, ftp://ftp.pentalogix.com/Updates/3DBoardViewer/ and the 64-bit version is here, ftp://ftp.pentalogix.com/Updates/3DBoardViewer64/. Once installed the utility can open 3D *.zip archives like this 3D edition of the same board.
  3. ZofzPCB is a promising 3D viewer, in development for about a year or so. There are 2 files to every project, a stackup file with extension *.camset and a project file with extension *.zofzproj. The utility can be downloaded from the zofzPCB website: https://www.zofzpcb.com/. As above, the same sample board is represented in this *.zip archive.
  4. In the remainder of this page the 2D icon you see below represents a 2D Gerbv project and the 3D icon represents a 3D Board Viewer project, all three icons are links to project design files. The filenames of the archives indicate the utility they are intended for, so "GERBV", "3D", and "3DZ" mean 2D Gerbv project, 3D Board Viewer project, and 3D zofzPCB project respectively.
Gerbv - 2D Gerber Viewer
3D Gerber Viewer
GERBV.CDi3M1.zip
3D.CDi3M1.zip
3D ZofzPCB Gerber Viewer
3DZ.CDi3M1.zip
2015-2018 - CDi4 Boards
CDi4 in active development since August 2015, component boards will be added in this section as the work progresses. Two memory boards have been added as of mid-June 2016, main board, charger, and keyboard/display boards yet to be created...
2016 - CDi4.M1 Storage Memory/EEPROM Board
2016 - CDi4.M2 Storage Memory/EEPROM Board
CDi4 Memory Module 1
CDi4 Memory Module 2
2016 - CDi3.P7 Main Board - One More Step Closer to CDi4
CDi3.FTe Submersible, Universal, Gas Field Controller
CDi3.P7 Main Board
  1. Clock increase from 6.144MHz to 7.373MHz resulting in a maximum baud rate of 115.2K for both communication channels.
  2. Ability to use the newer DS1553 RTC, since the DS1386 is now obsolete but still available in the aftermarket.
  3. Design preserves the original 8-channel analog circuitry, multiplexer is not used in digital modes, ADC only there to read the battery voltage.
  4. Added a Bluetooth wireless interface to the main communications channel.
  5. The CDi4 will be built as a general purpose industrial class controller as per lake Erie roadmap, the CDi4 is extremely unlikely to ever be used in the lake.
2016 - CDi3.LE Main Board - One Step Closer to CDi4
2016 - RS485 Board for the ZDL5
ZDL5 RS485 Board

P5RS485
Gerbv Design - P5RS485 Board
3D Design - P5RS485 Board
3D ZofzPCB Design - P5RS485 Memory Board
2010 - XTMASTER
2010 - Master Modem
2010 - Master Modem
2010 - P7MAIN, Charger and Memory Boards - On the Way to CDi4
CDi3.P7 Keller-Digital Switcher
Original P7MAIN Board
Lake Erie datalogging/control operations went digital in 2011 after the introduction of the prototype P7MAIN board and associated charger and memory boards. Five systems were built and subsequently installed by June 2011, some firmware bugs were discovered and corrected, all are alive and well today.

CPU
Clock
Heartbeat
On Time
Memory
Solenoids
Max. Baud
Z8S180
3.07MHz
2 Secs
3 Secs
1MB
2
38400


GERBV  Memory Board Design
3D  Memory Board Design
2010 Memory
GERBV Design - P7 NiMH Charger
3D Design - P7 NiMH Charger
2010 Charger
Gerbv Design - P7MAIN Board
3D Design - P7MAIN Board
2010 P7MAIN
3D zofzPCB Design - P7 NiMH Charger
3D zofzPCB  Memory Board Design
2000 - Now - CDi2 Boardsets
1999 - 2006 - PDL5/CDi1
1999 - 2006 PDL5 Board
P5 Flowmeter
Following a large purchase of 1000psi Viatran transmitters in '97 and the TF, Trustco Fiasco in '98, not to mention the computer world moving frantically from DOS to Windows, the PDL5 was built to make all those pressure transmitters usable.

CPU
Clock
Heartbeat
On Time
Memory
Solenoids
Max. Baud
NSC800N
3.07MHz
5 Secs
6 Secs
1MB
2
38400

P5
Gerbv Design - P5 Board
3D Design - P5 Board
3D ZofzPCB Design - P5 Board
1998 - PDL4
1998 - PDL4 Board
1998 - PDL4 Flowmeter
The PDL4 was built by summer 1998, its clock rate was subsequently increased and by 1999 its software moved from DOS to Windows. Afterwards the board was called "PDL5" despite the fact a real PDL5 board wasn't actually manufactured until 2006. So only cosmetic differences between PDL3 and PDL5 from the hardware point of view.

CPU
Clock
Heartbeat
On Time
Memory
Solenoids
Max. Baud
NSC800N
1.2MHz
10 Secs
11 Secs
1MB
2
9600
P4
Gerbv Design - P4 Board
3D Design - P4 Board
1997 - PDL3
1997 - PDL3 Board
1997 - PDL3 Flowmeter
The PDL3 was built by summer 1997 after pototyping a PDL1 board to switch two latching solenoids. So there was only one PDL2 and it was a prototype, two MOSFETS were added to a PDL1 board to control a second solenoid, here is a closeup.

CPU
Clock
Heartbeat
On Time
Memory
Solenoids
Max. Baud
NSC800N
1.2MHz
10 Secs
11 Secs
1MB
2
9600

P3
Gerbv Design - P3 Board
3D Design - P3 Board
1996 - PDL1
1996 - PDL1 Board
1996 - PDL1 Flowmeter
The first few prototype PDL1s were installed at lake bottom in November 1996. Unlike all the other devices that followed it, the PDL1 could only operate one latching solenoid.

CPU
Clock
Heartbeat
On Time
Memory
Solenoids
Max. Baud
NSC800N
1.2MHz
10 Secs
11 Secs
256KB
1
9600
P1
Gerbv Design - P1 Board
3D Design - P1 Board

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